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1/25 rev. b ???e structure silicon monolithic integrated circuit u? ?`? ?`?` ?`? structure power control & driver ic for portable cd q type q ? ???`? package outlines figure 1.plastic mold ?? ? block diagram figure 2. ? ? application circuit figure 3. y ? test circuit figure 4.
2/25 rev. b C ? feature ?M low power consumption ??? low on-resistance ??????` ssop-b40 package. ?`?`? power control section ?NR???`?? step up dc/dc converternpn,pnp tr is needed outside. ? `NR???i vg booster circuit for driving the power-mosswitching tr built-in. ? R?` voltage down regulator circuit. ???? reset circuit. ? driver section ??` ????????i 4 channels of power-mos h-bridge are contained ??? available for analog input. ???l?? direct pwm drive system.
3/25 rev. b ~?? absolute maximum ratings ta 25 parameter symbol limits unit ????R h-bridge power supply voltage pvcc 7 ??`??R battery power supply voltage rego 7 ???R system power supply voltage vsys 7 ????R ac adapter power supply voltage dc_in 7 ????R pre-driver power supply voltage vg 7 S?p? power dissipation pd 1000 ?? operating temperature range topr -30 85 ?? storage temperature range tstg -55150 *1pcb7.0mm7.0mm, 1.6mm ?g?r ta25??8.0mw Xp? *1reduce power by 8.0 mw for each degree above 25 , on a glass epoxy pcb (70mm 70mm,1.6mm thick). ?X recommended operating conditions parameter symbol min typ max unit ????R h-bridge power supply voltage pvcc 1.5 2.4 4.5 ??`??R battery power supply voltage rego 1.5 2.4 4.5 ???R system power supply voltage vsys 2.3 2.5 4.5 ????R ac adapter power supply voltage dc_in 3.0 4.5 6.5 ????R pre-driver power supply voltage 2 vg 5.0 6.0 6.9 ?? ambient temperature ta -10 25 70 *2iNR????o? *2the built-in booster circuit is not used, but the voltage is supplied from outside.
4/25 rev. b
5/25 rev. b ??? electric characteristics 2 ???? unless specified particularly ta=25, pvcc=rego=2.4v, vsys=2.5v, vg=6v, vref=1.25v parameter symbol min typ max unit condition circuit NR` up/down voltage converter section ei???R ei pin threshold voltage veith 0.84 0.905 0.97 v ? fig.4-1 eo??R eo pin output voltage h veoth 1.1 1.3 - v ieo=100a ? fig.4-1 eo??R eo pin output voltage l veol - - 0.4 v ieo=-60a ? fig.4-1 `???? s hort-circuit protection sprt?R ? sprt pin voltage (normal) vsprtn - - 0.2 v ? fig.4-1 sprt 1 eo = sprt pin current 1,eo=h isprt1 3.8 5.8 8.8 ua ? fig.4-1 sprt 2 offr sprt pin current 2,off mode isprt2 7.5 11.5 17.5 ua ? fig.4-1 sprt??` sprt pin impedance rsprt 210 300 390 k ? fig.4-1 sprt???R sprt pin threshold voltage vsprtth 0.4 0.5 0.6 v ? fig.4-1 ??`? soft start section soft??R soft pin output voltage vsoft 0.65 1.1 1.55 v ? fig.4-1 soft soft pin current isoft 3 6 9 ua soft=0.6v ? fig.4-1 soft??` soft pin impedance rsoft 140 200 260 k ? fig.4-1 ??`?` interface section off?????R off pin on threshold voltage voffth1 - - vsys-1.5 v ? fig.4-1 off????R off pin off threshold voltage voffth2 vsys-0.6 - - v ? fig.4-1 off? off pin bias current ioff 30 60 90 ua off=0v ? fig.4-1 start?????R start pin on threshold voltage vstath1 - - rego-1.0 v ? fig.4-1 start????R start pin off threshold voltage vstath2 rego-0.3 - - v ? fig.4-1 start ? start pin bias current istart 10 14 18 ua vsys=0v,start=0v ? fig.4-1 clk???R clk pin threshold voltage h vclkthh 1.5 - - v ct=470pf,fclk=88.2khz ? fig.4-1 clk???R clk pin threshold voltage l vclkthl - - 0.5 v ct=470pf,fclk=88.2khz ? fig.4-1 clk? clk pin bias current iclk 13 18 23 ua vclk=2.5v ? fig.4-1 ?O???? this product is not designed for protection against radioactive rays.
6/25 rev. b ??? electric characteristics 3 ???? unless specified particularly ta=25, pvcc=rego=2.4v, vsys=2.5v, vg=6v, vref=1.25v parameter symbol min typ max unit condition circuit ` starter circuit section lg?k? lg pin oscillating frequency flg 75 100 125 khz vg=lg=5v ? fig.4-1 lg? ????????? lg pin maximum pulse duty tlgmax 72 80 88 vg=lg=5v ? fig.4-1 lg??R lg pin output voltage l vlgl - 0.1 0.2 v vg=lg=5v ? fig.4-1 vg?`??R vg pin starter detect vvgstth 3.2 4.0 4.8 v vg=3v 5v sweep ? fig.4-1 vg???R vg pin threshold voltage vvgth 5.1 6.0 6.9 v lg=5v ? fig.4-1 ??` dc /dc converter sw??R sw pin output voltage h vswh 1.3 1.8 - v ct=0.2v,isw=5ma,ei=0.7v vsprt=0v ? fig.4-1 sw??R sw pin output voltage l vswl - 0.5 1.0 v ct=2v,isw=-1ma ? fig.4-1 sw?`r? sw pin oscillating frequency at start tswsta 75 100 125 khz vsys=1.6v,vg=5v ? fig.4-1 sw?k?? sw pin oscillating frequency (self-running) fsw1 36 48 60 khz ei=0.7v,ct=470pf,vsprt=0v ? fig.4-1 sw?k??? sw pin oscillating frequency (clk synchronization) fsw2 - 88.2 - khz ei=0.7v,clk=88.2khz,vsprt=0v ? fig.4-1 sw?`r?`? sw pin pulse duty at start dswsta 15 30 45 vsys=1.6v,vg=5v ? fig.4-1 ?r?`? sw pin oscillating maximum pulse dutyself-running dsw1 80 90 95 ei=0.7v,ct=470pf,vsprt=0v,clk=0v ? fig.4-1 clk??r?`? sw pin oscillating maximum pulse dutyclk synchronizat- ion dsw2 80 90 95 ei=0.7v,ct=470pf,vsprt=0v ? fig.4-1 ?k triangular wave generation circuit ct???R ct pin threshold voltage h ctthh 0.7 0.8 0.9 v ct=0.7v 1v sweep ? fig.4-1 ct???R ct pin threshold voltage l ctthl 0.34 0.4 0.46 v ct=0.5v 0.2v sweep ? fig.4-1 ct? ct pin sink current ictsin 80 92 104 ua ct=1.0v ? fig.4-1 ct? ct pin output current ratio hct 6.5 8 9.5 - sink current / source current ? fig.4-1 ?O???? this product is not designed for protection against radioactive rays.
7/25 rev. b ??? electric characteristics 4 ???? unless specified particularly ta=25, pvcc=rego=2.4v, vsys=2.5v, vg=6v, vref=1.25v parameter symbol min typ max unit condition circuit vsys circuit section ?`?R discharge release voltage vdis 1.40 1.51 1.62 v ? fig.4-1 ``? Q?R starter normal switching voltage vstn 1.64 1.75 1.86 v vsys=1.5v 2v sweep ? fig.4-1 `?` Q?R normal starter switching voltage vnst 1.56 1.67 1.78 v vsys=2v 1.5v sweep ? fig.4-1 ``? Q? starter normal switching hysteresis width vstnhis 40 80 120 mv vstn-vnst ? fig.4-1 ?? reset section ei????R? ei pin reset voltage threshold ratio hrst 80 85 90 ei ???R? ratio of ei pin threshold voltage ? fig.4-1 reset??R reset pin output voltage voreset - - 0.5 v ireset=-1ma ? fig.4-1 reset?` reset pin leak current ilkreset - - 2 ua vreset=2.5v ? fig.4-1 ?` regulator circuit section ?`?R regulator output voltage vreg 2.9 3.2 3.5 v rego=open,dc=in=6v ? fig.4-1 regb ??R regb pin output voltage voregb - - 1.4 v dc_in=6v,iregb=10ma ? fig.4-1 regb ?` regb pin leak current ilkregb - - 3 ua rego=3.5v,dc_in=6v,regb=6v ? fig.4-1 regb ??? regb pin limit current ilmregb 10 15 20 ma dc_in=6v ? fig.4-1 dc_in p??`???R dc_in low-voltage mute on voltage vdc_inlv - - 1.3 v dc_in ? dc_in voltage ? fig.4-1 dc_in p ?`??R dc_in low-voltage mute off voltage vdc_inof 1.9 - - v dc_in ? dc_in voltage ? fig.4-1 ?O???? this product is not designed for protection against radioactive rays.
8/25 rev. b
9/25 rev. b ? ?? figure.2 block diagram vg conv dc/dc converter reg pre-dr pre-dr pre-dr pre-dr system off mute34 system on osc clk vsys 30k 30k mute1 reset 30k 30k start mute34 mute1 reset vref fil1 fil2 fil3 fil4 pgnd1 out4- out4+ out3- out3+ vsys pgnd3 rego regb dc soft sprt pgnd2 out1+ out1- out2+ out2- pvcc 40 39 38 37 36 35 34 32 31 30 33 29 28 27 26 25 24 23 22 21 eo ei sw vg lg gnd - in ct 1 2 3 4 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 6 off clk in1 in2 in3 in4
10/25 rev. b h descriptions of terminals no. h no. h start dc/dc`? dc/dc converter starting terminal pvcc ?`? h-bridge power supply input terminal off dc/dc `off dc/dc converter off terminal out2- ch2 ? ch2 negative output clk ?? external clock synchronization input terminal out2+ ch2 ch2 positive output mute34 ch3,4 ?`? ch3,4 mute terminal out1- ch1 ? ch1 negative output mute1 ch1 ?`? ch1 mute terminal out1+ ch1 ch1 positive output reset ??? reset output terminal pgnd2 ?`? power unit power supply ground terminal 2 in1 ch1 ch1 input terminal sprt ?`?rO short-circuit protection setting terminal in2 ch2 ch2 input terminal soft ??`O soft-start setting terminal in3 ch3 ch3 input terminal ct ? triangular wave output terminal in4 ch4 ch4 input terminal dc - in ac?? ac adapter power supply input terminal vref ?R reference power supply input terminal regb ?`trl? tr driving terminal for regulator fil1 ch1 ?? ch1 feedback filter terminal rego ??`? battery power supply input terminal fil2 ch2 ?? ch2 feedback filter terminal gnd ?? pre-unit power supply ground terminal fil3 ch3 ?? ch3 feedback filter terminal pgnd3 ?`? power unit power supply ground terminal 3 fil4 ch4 ?? ch4 feedback filter terminal lg vgNR?l? drive coil for boosting vg terminal pgnd1 ?`? power unit power supply ground terminal 1 vg ?`mosl?? drive the power-mos circuit power supply input terminal out4- ch4 ? ch4 negative output sw NR????l? booster transistor drive terminal out4+ ch4 ch4 positive output vsys ?`? control circuit power supply input terminal out3- ch3 ? ch3 negative output ei dc/dc `` dc/dc converter error amplifier input terminal out3+ ch3 ch3 positive output eo dc/dc `` dc/dc converter error amplifier output terminal
11/25 rev. b 40 39 38 37 36 35 34 32 31 30 33 29 28 27 26 25 24 23 22 21 vg conv dc/dc converter reg vsys detect pre-dr pre-dr 1 2 3 4 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 pre-dr pre-dr system off mute34 system on osc clk vsys 30k 30k mute1 6 reset 30k 30k start off clk mute34 mute1 reset in1 in2 in3 in4 vref fil1 fil2 fil3 fil4 pgnd1 out4- out4+ out3- out3+ eo ei vsys sw vg lg pgnd3 gnd rego regb - dc_in ct soft sprt pgnd2 out1+ out1- out2+ out2- pvcc off mute34 clk clv jumpo tracking focus sled vref tracking focus 0.022 f com m m sled spindle 1 0.1 470p 220 100 dc/dc converter application 8.2k 0.022 10k 20k 10 vreg =3.2v dc_in 18k 33k dsp 10 z-di 7v(max) rin rin rin mute1 reset servo power supply 330 10 0.022 f 0.022 f 0.022 f ? ? figure.3 application circuit ??? equivalent circuit diagram 1
12/25 rev. b pin no. terminal name explanation equivalent circuit diagram 1 start dc/dc `?? dc/dc converter starting terminal. 2 off dc/dc ` off? dc/dc converter off terminal. 3 clk ???? 88.2khz ??? gnd `? external clock synchroni- zation input terminal. input 88.2khz pulse. to allow self-advancing operation, make it short to gnd. 4 mute34 ch3,4 ?`?? ch3,4 mute terminal. 5 mute1 ch1 `?? ch1 mute terminal. 390k rego 220k rego start vsys off vsys 100k 30k vsys clk 150k 100k vsys mute34 150k 100k vsys mute1 150k 100k
13/25 rev. b ??? equivalent circuit diagram 2 pin no. terminal name explanation equivalent circuit diagram 6 reset ???? reset output terminal. 7 8 9 10 in1 in2 in3 in4 ? pwm driver input terminal. 11 vref ?R? reference power supply input terminal. 12 13 14 15 fil1 fil2 fil3 fil4 ??? feedback filter terminal. vsys vsys 100k 100 reset vsys vsys 100 30k 8 7 9 10 vsys 10k 15k 40k 37k 20k 10p 120k vref 12 13 14 15 vsys 20k 20k 1k vsys 2k vsys
14/25 rev. b ??? equivalent circuit diagram 3 pin no. terminal name explanation equivalent circuit diagram 16 17 18 19 20 21 pgnd1 out4- out4+ out3- out3+ pvcc ? ch3,4 ? pwm driver ch3,4 output terminal. 21 22 23 24 25 26 pvcc out2- out2+ out1- out1+ pgnd2 ? ch1,2 ? pwm driver ch1,2 output terminal. 27 sprt `?oO? gndg?????? short-circuit protection setting terminal. please connect capacitor to gnd. 28 soft ??`O? gndg ????? soft-start setting terminal. please connect capacitor to gnd. 29 ct ?? gndg????? triangular wave output terminal . please connect capacitor to gnd. ??? equivalent circuit diagram 4 21 19 17 20 18 16 120k 120k 120k 120k 21 24 22 35 23 26 120k 120k 120k 120k ct vsys vsys soft vsys 2k 200k vsys sprt vsys 300k vsys
15/25 rev. b pin no. terminal name explanation equivalent circuit diagram 30 dc-in ac??? ac adapter power supply input terminal. 31 regb ?`???? l???pnp? ???`?? tr driving terminal for regulator. please connect the base of externally installed pnp tr to it. 32 rego ???? battery power supply input terminal. 33 gnd ?? pre-unit power supply ground terminal. 34 pgnd3 ?` NR power unit power supply ground terminal 3. (step up converter section) 35 lg vgNR?? ???? pvcc1 ?? switching transistor output for boosting the vg. connect the coil to it. 36 vg ?`mosl? ?? vg booster circuit for driving the power-mos. 37 sw NR`?? ?A? booster tr drive terminal. 38 vsys ?NR?? input of main dc/dc converter power source. regb 47 lg vg rego sw rego 50 500
16/25 rev. b ??? equivalent circuit diagram 5 pin no. terminal name explanation equivalent circuit diagram 39 ei `? dc/dc`?RO ?? error amp input. the terminal for setting the voltage of dc/dc converter. 40 eo `?? `?? Q? ei????? error amp output. the frequency characteri- stics of error amp can be determined. put the feedback constant to the ei. eo vsys vsys 1k ei vsys
17/25 rev. b ? y?? figure 4-1. test circuit 1 (circuit current, power section) dc/dc converter reg pre-dr pre-dr pre-dr pre-dr system off mute34 system on osc clk vsys 30k 30k mute1 reset 30k 30k eo ei vsys sw vg lg pgnd3 gnd rego regb dc - in ct soft sprt pgnd2 out1+ out1- out2+ out2- pvcc vg conv 40 39 38 37 36 35 34 32 31 30 33 29 28 27 26 25 24 23 22 21 st29 a 2 3 470p vct am29 st28 st27 1 23 4 a 300k sprt am27 am28 a soft 2 1 175k vm32 am32 dc - in a am30 rego 30k am31 1 2 34 st31 st32 v 2 1 5 iregb regb ireg 3.8v a a 200 1k ?` ? 1 vm35b fc35 lg 21 a am35 1 2 3 st37 10k 1.0v isw 4 ?` ? fc37 st35 vg am36 a vsys am38 a st40 2 1 ieo eo 1 30k 30k 30k 30k vref 0.022 f 0.022 f 0.022 f 0.022 f a start am1 a am2 off st3 f=88.2khz 0.5v/1.5v a am4 mute 34 a am5 mute1 st6 am6 2 3 reset 1 2 st1 am3 clk 2 1 3 ires a a 7 8 9 10 11 12 13 14 15 16 17 18 19 20 in1 in2 in3 in4 vref fil1 fil2 fil3 fil4 pgnd1 out4- out4+ out3- out3+ start off clk mute34 mute1 reset v 1 2 3 4 5 6 1
18/25 rev. b y??? table of measure circuit switch position 1 ???? unless specified particularly st=1, pvcc=rego=2.4v, vsys=2.5v, vg=6v, vref=1.25v, mute1=0.5v, mute34=1.5v cir- 1 3 6 2728293132353740 ei ct clk start off cuit iregost * 2 7 v * fig.4-1 am32 ivgst * 2 7 v * am36 irego 23 1.1v 2v 2.4 v am32 idc_in 1.1v am30 ivsys 3 1.1v 2v am38 ivg 32 0.7v pulse vin=1.49 v am36 ilglk * 2 mute1,34=0v,vref=open am35 veith * sweep fig.4-1 vm40 veoth 2 0.7v ieo=100a fig.4-1 vm40 veol 1.1v ieo=-60a vsprtn 3 1.1v fig.4-1 vm27 isprt1 2 0.7v am27 isprt2 2 1.1v 0 v am27 rsprt * 4 sprt=0.6v vm27*300k/(0.6-vm27) vsprtth * 2 0.7v 0.2 v fig.4-1 vm37 vsoft fig.4-1 vm28 isoft soft=0v am28 rsoft * 2 soft=0.6v vm28*175k/(0.6-vm28) voffth * 33 0.2 v * eo=1 v fig.4-1 vm37 ioff 0 v fig.4-1 am2 vstath * 2* * vsys=1.6v vm37 istart 2 0 v vsys=0v fig.4-1 am1 iclk 2 2.5 v am3 flg 2 1.1v vg=lg=5 v fig4-1 fc35 tlgma x 2 vlgl * 2 0.7v vvgstth * 33 0.7v 0.2 v fig4-1 vm37 vvgth * 2 lg=5 v fig4-1 vm35b vm35b terminal shall be "h" at vg=6.9v , vm35b terminal shall be "l" at vg=5.1v. <` starter circuit section> * lg?"l"???k?????R???R??? "l" level voltage of lg terminal (always oscillating) should be less than limit. * vg?3v??sw(vm37)"hi-z""l"???rvg?R sw terminal shall be "h" at sprt=0.4v, sw terminal shall be "l" at sprt=0.6v ei terminal voltage when eo terminal varies from "h""l" upo n increasing the ei voltage from 0.8v. vg terminal voltage when sw terminal (vm37) varies from "hi- z""l" upon increasing the vg voltage from 3v. * vg=6.9vvm35b"h"vg=5.1vvm35b"l"???_J * rego=vg=7v, vsys=0v, vref=open, mute1,34=0v sw terminal shall osc illate with 100khz at start=rego-1.0v (st:4), sw terminal shall be "hi-z" at start=rego-0.3v (st:3) * off=vsys-0.6vsw?"h"off=vsys-1.5vsw?"l"???_J * start=rego-1.0vsw?100khz?k(st:4)start=rego-0.3vsw?"hi -z"(st:3)???_J <`???? short-circuit protection> * rego=vsys=vg=0v, vref=mute1,34=open * ei?R0.8v??eo?R"h""l"??rei?R * rego=vsys=vg=0v, vref=mute1,34=open * rego=vg=lg=7v, vsys=0v, vref=mute1,34=0v < circuit current> measure point sw terminal shall be "h" at off=vsys-0.6v, sw terminal shall be "l" at off=vsys-1.5v paraeter st input * sprt=0.4vsw?"h"sprt=0.6vsw?"l"???_J condition
19/25 rev. b y??? table of measure circuit switch position 2 ???? unless specified particularly st=1, pvcc=rego=2.4v, vsys=2.5v, vg=6v, vref=1.25v, mute1=0.5v, mute34=1.5v cir- 1 3 6 2728293132353740 ei ct clk start off cuit vswh 32 0.7 v 0.2 v isw=5ma fig4-1 vm37 vswl 2 v isw=-1ma tswsta 4 vsys=1.6v, vg=5 v fc37 fsw1 2 0.7 v fsw2 3 pulse dswsta vsys=1.6v, vg=5 v dsw1 2 0.7 v dsw2 3 pulse ctthh * 3 0.7 v sweep fig4-1 vm37 ctthl * 3 0.7 v sweep fig4-1 vm37 ictsin 3 0.7 v 1 v fig4-1 am29 ictsou 0.2 v hct ictsou/istsin vdis * 0.7 v fig4-1 vm28 vstn 233 0.7 v 0.2 v 2.1 v fig4-1 vm37 vnst 233 0.7 v 0.2 v 2.1 v fig4-1 vm37 vstnhi s fig4-1 vstn-vnst hrst * * fig4-1 vm6 voreset 2 * * veith*0.8, ires=-1ma fig4-1 vm6 ilkreset 3 * * veith*0.9, reset=2.5v am6 vreg 22 rego=open,dc_in=5v, ireg=100ma fig4-1 vm32 voregb 3 dc_in=6v, iregb=-10ma vm31 ilkregb 4 dcin=6v, rego=3.5v, regb=6v am31 ilmregb * 3 dc_in=6v vm31 vdc_inlv 5 dc_in=1.3v fig4-1 vm32 vdc_inof dc_in=1.9v vm31 soft terminal (vm28) shall be "h" at vsys=1.62v, soft termin al shall be "l" at vsys=1.4v. * vsys=1.62vsoft(vm28)"h"vsys=1.4vsoft(vm28)"l"???_ J * vsys?1.5v???r?sw?R(vm37)"hi-z""h"??rvsys?R vsys terminal voltage when sw terminal (vm37) varies from "h i-z""h" upon increasing the ct voltage from 1.5v. regb terminal (vm31) shall be "l" at iregb=-10ma, regb termi nal shall be "h" at iregb=-20ma. * iregb=-10maregb(vm31)"l"iregb=-20maregb(vm31)"h"?? ?_J * ct?0. 7v???r?sw?R(vm37)"h""l"??rct?R ct terminal voltage when sw terminal (vm37) varies from "l" "h" upon decreasing the ct voltage from 0.5v. ct terminal voltage when sw terminal (vm37) varies from "h" "l" upon increasing the ct voltage from 0.7v. * ct?0. 5v??r?sw?R(vm37)"l""h"??rct?R measure point paraeter st input condition * vsys?2v??r?sw?R(vm37)"h""hi-z"??rvsys?R vsys terminal voltage when sw terminal (vm37) varies from "h ""hi-z" upon decreasing the ct voltage from 2v. * reset=veith*0.9vreset(vm6)"h"reset=veith*0.8vreset(vm 6)"l"???_J reset terminal (vm6) shall be "h" at ei=veith*0.9v, reset te rminal shall be "l" at ei=veith*0.8v.
20/25 rev. b ? y?? figure 4-2. test circuit 2 (driver section) 40 39 38 37 36 35 34 32 31 30 33 29 28 27 26 25 24 23 22 21 dc/dc converter reg pre-dr pre-dr 1 2 3 4 5 11 12 13 14 15 16 17 18 19 20 pre-dr pre-dr system off mute34 system on osc clk vsys 30k 30k mute1 6 reset 30k 30k start off clk mute34 mute1 reset in1 vref fil1 fil2 fil3 fil4 pgnd1 out4- out4+ out3+ eo ei vsys sw vg lg pgnd3 gnd rego regb dc - in ct soft sprt pgnd2 out1+ out1- out2+ out2- pvcc vref 0.022 f 0.022 f 0.022 f 0.022 f vsys vg rego dc - in vg conv 7 8 9 10 in2 in3 in4 30k vin1 30k vin2 30k vin3 30k vin4 out- out+ ch4 out3- out- out+ ch3 out- out+ ch2 out- out+ ch1 mute34 mute1 out- out+ ch1,2,3,4 out v 1 1 2 1 1k 1k 1f 1f 8 47h 21 1 2 il vo 2 2 sta sta stb stc std
21/25 rev. b y??? table of measure circuit switch position 2 ???? unless specified particularly st=1, pvcc=rego=2.4v, vsys=2.5v, vg=6v, vref=1.25v, mute1=0.5v,mute34=1.5v, ct=470pf *1 ?R voltage gain *2 ? input dead zone ch1,2 ?R-50mv ???r? ??g????? input dead zone is the interval of no output upon increasing input voltage from -50mv. ch3,4 ?R -30mv ???r? ??g????? input dead zone is the interval of no output upon increasing input voltage from -30mv. Ch explanations of function input abcd vin ron out+ top 2 2 2.5v il=-500ma fig1-2 pvcc-vout+ ron out+ bottom 0v il=500ma vout+ ron out- top 0v il=-500ma pvcc-vout- ron out- bottom 2.5v il=500ma vout- voo 2 2 1.25v vo vin=vref50mv,100mv * ? see below vdb *2 * ? see below vo vo gvc *1 measure point cir- cuit paraeter condition st ? input dead zone 50mv 100mv vin vo -100mv -50mv vo2 vo1 vo3 vo4 gvc+=20log( ) vo2-vo1 50mv gvc-=20log( ) |vo4-vo3| 50mv
22/25 rev. b ??`vsys dc/dc convertervsys ?? , ??R???? ?RO??? to set the output voltage, use the following r 1 and r 2. vsys 0.905 ?`l?NR`vg booster circuit for driving the power-mos vg i?`???l?????R? lg ??k?????`?`? ????? ?r?????? this unit can generate the vg voltage necessary for driving the built-in power-mos transistor. lg terminal oscillation frequency is independent and different from that of the main dc/dc converter. when start-up, this circuit activates at first. R?` down voltage regulator circuit ?`?? ? ????? output vsys dc/dc converter control eo 0.905v vsys rego input r 1 r 2 ei batt unreg dc/dc converter application sw triangular vg lg 330h rego pvcc1 unreg
23/25 rev. b ??`???? ?`?R?i?Q?? 3.2typ ? ?`?M?`??? the dc_in is the power source of regulator circuit. if pnp transistor is externally attached, it allows the regulator circuit with the rego set as the output voltage. output voltage is 3.2v, this regulator output voltage depends on the built-in resistance. it is unable to control on/off of this regulator. ??` soft start ??? gnd g????????C?? install the condenser between soft terminal and gnd, so that this function may act. rego dc-in regb dc jack
24/25 rev. b `?o short protective circuit sprt ?R? 0.5v ?sw ?37 ????????? ????`????? ?????sprt ???????? if the voltage of sprt terminal (pin 27) has reached 0.5v, switching of sw terminal (pin 37) is disabled. the main dc/dc converter can be tuned off only through the acti vation of timer latch circuit. accordingly be sure to attach the capacitor on the sprt termina l. `? eo v??gsprt ??? ????rg?sprt ????????Q?? while the error amp output of eo is being completely set at ? h ? , sprt terminal can be charged. the time until stopping the switching is determined by the foll owing formula for the capacitor of sprt terminal. t c sprt sec v th 0.5vi sprt 5.8a off ? vsys1.5v ?R????? sprt ??? ?????rg?sprt ????????Q?? while the off terminal is being set at below vsys-1.5v, sprt te rminal can be charged. the time until stopping the switching is determined by the foll owing formula for the capacitor of sprt terminal. t c sprt sec v th 0.5vi sprt 11.5a ? pwm driver ??????????? vref ?R?~ ??O??`???? ?`???????l?? ????R??????`?R??o???? h-bridge driver using 4 pieces of n-channel mos transistor on output stage. polarity of output and pwm duty are changed in proportion to differential voltage and absolute value of input sandwiching vref. load is direct-pwm driven by square wave of this changing duty. this driver is voltage feedback type, so, voltage gain is invariable in spite of fluctuation of battery voltage. `???? thermal shut down ??? 150typ.??????? ????? 130typ. ????? when the chip temperature has been 150 (typ.), the output current is muted. and when the chip temperature has dropped to 130 (typ.), the driver circuit starts up. sprt th sprt th
25/25 rev. b ??? note in use o?g???? 0.1f ???? between power supplies, attach a by-pass capacitor (approx. 0.1f) at the root of this ic. ?????R???? ?`?????R gnd ??` ??]?? in principle, do not apply voltage below sub-potential of ic to terminal. examine in consideration of operation margin, when each driver output falls below sub-voltage of ic (gnd) due to counter-electromotive-force of choke coil, etc. ?vcc g`?j ?gnd g`??j ??g`?? ?`???? ???H???????? output pin is to avoid short-circuiting with pvcc, gnd, and other output pins. and, be fully careful in the direction of an integrated circuit on the substr ate. ????r? dc_in 7v ??R??? z-di ?A dc_in ? 7v ???? ?o dc_in 7.5v(typ.)??R??sprt ?? (i sprt 11.5a`?o?) when use ac adapter, if apply beyond 7v to dc_in pin, connect z-di with dc_in pin. so keep voltage of dc_in being below 7v. to protect ic, once the voltage to be applied on the dc_in terminal exceeded 7.5v(typ.), sprt terminal can be charged.(isprt11.5a, see short protectiv e circuit ) start ?? rego-1.0v ?R???off ?? vsys-1.5v ?R? ?r ? please do neither voltage impression of rego-1.0v or less to start pin, nor the voltage impression of vsys-1.5v or less to off pin at the same time.
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